JPH0559614B2 - - Google Patents
Info
- Publication number
- JPH0559614B2 JPH0559614B2 JP58238598A JP23859883A JPH0559614B2 JP H0559614 B2 JPH0559614 B2 JP H0559614B2 JP 58238598 A JP58238598 A JP 58238598A JP 23859883 A JP23859883 A JP 23859883A JP H0559614 B2 JPH0559614 B2 JP H0559614B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- output
- divider
- frequency divider
- synthesizer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000010355 oscillation Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000010295 mobile communication Methods 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/185—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using a mixer in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58238598A JPS60130218A (ja) | 1983-12-16 | 1983-12-16 | 周波数シンセサイザ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58238598A JPS60130218A (ja) | 1983-12-16 | 1983-12-16 | 周波数シンセサイザ |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60130218A JPS60130218A (ja) | 1985-07-11 |
JPH0559614B2 true JPH0559614B2 (en]) | 1993-08-31 |
Family
ID=17032569
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58238598A Granted JPS60130218A (ja) | 1983-12-16 | 1983-12-16 | 周波数シンセサイザ |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60130218A (en]) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6878650B2 (en) | 1999-12-21 | 2005-04-12 | Kimberly-Clark Worldwide, Inc. | Fine denier multicomponent fibers |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2552840B2 (ja) * | 1986-10-31 | 1996-11-13 | 八重洲無線 株式会社 | Pll回路 |
US6806746B1 (en) * | 2003-07-31 | 2004-10-19 | Agilent Technologies, Inc. | Direct frequency synthesizer for offset loop synthesizer |
-
1983
- 1983-12-16 JP JP58238598A patent/JPS60130218A/ja active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6878650B2 (en) | 1999-12-21 | 2005-04-12 | Kimberly-Clark Worldwide, Inc. | Fine denier multicomponent fibers |
Also Published As
Publication number | Publication date |
---|---|
JPS60130218A (ja) | 1985-07-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2526847B2 (ja) | ディジタル方式無線電話機 | |
JP2003198366A (ja) | 周波数シンセサイザ及び移動端末装置 | |
US7170965B2 (en) | Low noise divider module for use in a phase locked loop and other applications | |
CN102307049B (zh) | 无线发送电路以及利用该电路的收发机 | |
US6094569A (en) | Multichannel radio device, a radio communication system, and a fractional division frequency synthesizer | |
US6066990A (en) | Frequency divider having a prescaler followed by a programmable counter, and a corresponding prescaler and frequency synthesizer | |
JPH01126023A (ja) | 送受同時通信無線機 | |
WO2004021572A2 (en) | Multiple band local oscillator frequency generation circuit | |
JP2807703B2 (ja) | 信号発生装置 | |
JP2003087116A (ja) | Pllシンセサイザ | |
JPH0559614B2 (en]) | ||
US5907590A (en) | Frequency dividing circuit, frequency dividing method and telephone terminal device incorporating the frequency dividing circuit | |
CN115208384B (zh) | 一种低杂散dds扩频装置及方法 | |
EP0943180A1 (en) | Multichannel radio device, a radio communication system, and a fractional division frequency synthesizer | |
JP2000357966A (ja) | 周波数シンセサイザ | |
JP3556917B2 (ja) | 周波数シンセサイザ | |
JP3120973B2 (ja) | ダブルスーパヘテロダイン式受信方法とその受信回路 | |
US7020230B2 (en) | Frequency synthesizer for dual mode receiver | |
Peng et al. | A 24-28 GHz Frequency Synthesizer for 5G Applications | |
JPH1188164A (ja) | 周波数シンセサイザ | |
Wu et al. | A CMOS triple-band fractional-N frequency synthesizer for GSM/GPRS/EDGE applications | |
JP3596172B2 (ja) | Pll周波数シンセサイザ | |
JPH03148916A (ja) | 周波数シンセサイザ装置 | |
WO2022041277A1 (zh) | 锁相环和射频收发机 | |
JP2006101168A (ja) | 周波数シンセサイザ |